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7 Tips for Overcoming PCB
Electromagnetic Issues

Zulki
Khan, NexLogic
7/28/2015 09:17
AM EDT
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Faced with the challenges of new materials and new components,
PCB designers must also deal with continuing electromagnetic
compatibility and interference problems.

Tip #4: Decoupling
capacitors
Decoupling capacitors reduce crosstalk’s
undesirable effects. They should be placed between the power pin and
ground pin of a device, which ensures low AC impedance for reducing
noise and crosstalk. To reach low impedance over a wide range of
frequency, several decoupling capacitors should be used.

Decoupling capacitors around a ball grid
array reduces crosstalk effects
(Source: NexLogic)

An important decoupling capacitor placement rule is to place the
lowest value capacitor as close to the device as possible to reduce
the inductive effect on the trace. Place this particular capacitor
as close as possible to the device’s power pin or power trace and
directly connect the capacitor’s pad to the via or ground plane. If
the trace length is long, use more than one via to achieve the
lowest impedance connection to ground.

Tip #5: Avoid 90° angles
To reduce EMI it’s
important to avoid 90° angles for traces, vias, and other components
because right angles cause radiation. Here, capacitance increases in
in that corner and characteristic impedance changes causing
reflection, which in turn causes EMI interference. To avoid 90°
angles, traces should be routed at least on two 45° angles to the
corners.

Tip #6: Use vias with care
Using vias for
conductive connections between different layers is essential in
virtually any PCB layout. However, the PCB layout engineer needs to
take special care when using them because vias create inductance and
capacitance. In some instances, they create reflections because the
characteristic impedance changes when a via is made in a trace.

It’s also important to remember that a via increases trace
length, which needs to be matched. Avoid vias as much as possible if
it’s a differential trace. If that’s impossible, then vias need to
be used in both traces to compensate for the delay like in the
signal and return paths.

Tip #7: Cables and physical shields
Cables
carrying digital circuits and analog currents cause most EMC-related
issues by creating parasitic capacitance and inductance. If twisted
pair cable is used, it keeps coupling to a lower level and cancels
any generated magnetic fields. For high-frequency signals, a
shielded cable is essential, connected to ground at the front and
back, which cancels whatever EMI interference is present.

Physical shields are metallic packages that cover all or part of
a system and play a major role in keeping EMI from entering into the
PCB’s circuitry. Depending on design requirements, these shields
act like closed conductive containers connected to ground they
reduce antenna loop size and absorb EMI.

-- Zulki Khan is the founder and president of NexLogic Technologies, a PCB manufacturer
specializing in ISO 9001:2008 and ISO 13485 designs that are RoHS
compliant. He received a B.S.E.E from N.E.D University and an M.B.A
from University of Iowa, and has also worked on high-speed PCB
designs requiring rigorous signal integrity
analysis.

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Re: Tip #1 - Huh?
Allramified
8/3/2015 5:26:01 AM

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The
author need to update himself on the topic. Much water has
flown under the bridges since these rules were considered to be
valid. Several of them have also no evidence of being true, they're
just old practice without anyone knowing how and
why.

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Re: Tip #1 - Huh?
anon9303122
7/31/2015 3:52:00 PM

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Yes,
me too.   They put on a great seminar.  I was
saddened when they were putting up all their equipment for
sale.

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Re: Tip #1 - Huh?
Paul
Bryson   7/31/2015 2:17:51 PM

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I
was very sad to read that Bill Kimmel died earlier this year.
I have learned a great deal from his writing over the
years.

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Re: Tip #1 - Huh?
anon9303122
7/31/2015 12:50:06 PM

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Kimmel
and Gerke would take exception to many things in this article.
This is written by someone who knows just enough anecdotal 'tips' to
be dangerous.  Run away, run away.

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Re: Tip #1 - Huh?
Howman
7/29/2015 11:27:31 AM

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Articles
like this only reinforce the false notion that designing for
EMC is a black art.

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Re: Tip #1 - Huh?
boblespam
7/29/2015 3:06:00 AM

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I
confirm, splitting ground plane is a bad idea as you'll have nets
crossing the different planes boundaries which is very bad for the
given signal integrity and radiation.

90° angles only have an
impact on very high speed signal (steep fronts), most of the time it
has no impact on EMI.

"Decoupling capacitors reduce
crosstalk's undesirable effects": crosstalk beetween what and what
?

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Tip #1 - Huh?
Paul
Bryson   7/28/2015 5:44:14 PM

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Referring
to the paragraph in Tip #1, beginning, "The length of signal returns
to ground is highly important," and ending, "If source and return
path aren't about equal in length, ground bounce, another form of
EMI, is produced."

I can't make sense of this paragraph.
Previous paragraphs were about ground planes. Is this
paragraph talking about a signal and it's return path through the
ground plane?  The diagram seems to show return traces
surrounding a signal trace.  For EMI what matters is that the
signal and return path stay physically close together, minimizing
the loop area and the inductance.  The fact that the return
time matches the outgoing time is incidental.

The
phenomenon of "ground bounce" is usually caused when an IC tries to
quickly sink a large pulse of current into ground from an output pin
or from the supply and inductance in the ground path causes a
localized rise in the ground voltage.  What "ground bounce" is
the author referring to? In the return trace? If so then this would
again be about minimizing inductance - not matching
timing.

In another paragraph the author recommends splitting
the ground plane.  This is rarely good advice and should never
be done without following a large number of other "rules".
Otherwise, EMI will be made worse instead of
better.

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Tip #6: Use vias with care
zeeglen
7/28/2015 10:20:02 AM

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Also
remember to place an closely adjacent via connecting the power
planes wherever a high-speed via occurs.

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