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Blog

7 Tips for Overcoming PCB
Electromagnetic Issues

Basic
tips on deal with board-level EMI and EMC

Zulki
Khan, NexLogic
7/28/2015 09:17
AM EDT
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Faced with the challenges of new materials and new components,
PCB designers must also deal with continuing electromagnetic
compatibility and interference problems.

Electromagnetic compatibility (EMC) and
related electromagnetic interference (EMI) are two culprits system
design engineers have historically kept a sharp eye on, among their
myriad of other problematic areas. In particular, both are hampering
PCB layout and design engineers, especially today as board designs
and component packaging continue shrinking and OEMs demand
higher-speed systems.

EMC is associated with the generation, propagation, and reception
of electro-magnetic energy — not exactly a welcomed character in a
PCB design. That energy results due to a mixed combination of energy
producers and care must be taken to make sure such signals are
compatible and do not interfere with each other when it is necessary
that different circuits, traces, vias, and PCB materials operate in
unison.

EMI, on the other hand, are the unwanted, damaging effects EMC or
the undesirable energy generates. In such an electromagnetic
environment, the PCB designer’s goal is to assure that various
energy elements are reduced to maintain minimal interfering
effects.

Here are some tips on how to avoid these problems in your printed
circuit board design.

Tip #1: Take it to ground
Designing a PCB’s
ground plane is the most important part of reducing EMI. The first
step is to increase as much as possible the PCB’s ground area within
the board’s total area, which reduces emissions, crosstalk, and
noise. Care should be taken to connect each component to a ground
point or plane. If that’s not done, the neutralizing effect of a
solid ground plane provides isn’t being fully utilized.

A highly complex PCB design is characterized by several regulated
voltages. Ideally, every reference voltage should possess its
corresponding ground plane. However, an excessive number of ground
planes could increase the PCB fabrication cost, making it overly
expensive. A compromise measure is to split the ground planes at
three to five different places, accommodating multiple ground
sections in one ground layer. This keeps the cost of board
fabrication cost in check while reducing EMI and EMC.

A low impedance ground system plays a big role in minimizing EMC.
In a multi-layer PCB it’s best to have a solid ground plane versus
copper thieving or hashed ground planes since it offers both a lower
level of impedance with the current path serving as the backward
source at its optimum level.

To
deal with EMC problems in a multi-layer PCB, it is best to have a
solid ground plane versus copper thieving or hashed ground
planes.

The length of signal returns to ground is highly important, as
well. The amount of time a signal takes to and from the source must
be compatible; otherwise, an antenna-like phenomenon is created that
radiates energy as part of EMI. Also, traces transmitting current to
and from the source should have paths as short as possible. If
source and return path aren’t about equal in length, ground bounce,
another form of EMI, is produced.

If
the amount of time a signal takes to and from its source is not
carefully synchronized, an antenna-like phenomenon is created that
radiates energy as part of EMI.

Tip #2: Compartmentalize EMI
Because there
are different segments to EMI, a good EMC design rule is to focus on
analog and digital circuitry separately. Analog circuits carry
relatively high amperage or high current and should be kept away
from high-speed traces or switching signals. If at all possible,
they should be guarded with a ground signal. On a multi-layer PCB,
routing analog traces there is should be a ground plane between them
and the switching or high-speed traces should be on a different
plane. Therefore, these signals, which have different
characteristics, stay separately.

Sometimes a low pass filter can be included to eliminate high
frequency noise coupled from surrounding traces. The filter
suppresses the noise, allowing a stable current to continue on the
return patch. It’s important to keep the ground planes for the
analog and digital signals separate. Separation is critical due to
the unique characteristics of analog and digital circuitry. The
digital signal should have a digital ground, and the analog signal
should be terminated at an analog ground.

In digital circuitry design, savvy PCB layout and design
engineers pay careful attention to high-speed signals and clocks. At
high-speed levels, signals and clocks should be kept as short as
possible and adjacent to the ground plane because, as noted earlier,
the ground plane keeps crosstalk, noise, and radiation levels in
check and within the acceptable level limits.

Digital signals should also be kept away from the power plane.
If they’re close to it they can create noise or induction, thereby
deteriorating the signal and weakening it.

Tip #3: Place emphasis on crosstalk and
traces
Traces are especially important to ensure that
current is properly propagated. This is particularly true if
current is coming from an oscillator or some other similar device to
keep the current separated from the ground plane or another trace
not running in parallel. Two high-speed signals running in parallel
create EMC and EMI, in particular crosstalk. Keep the return current
path as short as possible with the least resistive path. Return path
traces should be about the same length as the transmit traces.

When it comes to EMI, one trace is called the “aggressor,” while
the other is the “victim.” An inductive and capacitive coupling
influences the victim trace as a result of an electromagnetic field,
creating forward and backward current in the victim trace. This
creates a ripple in the stable environment whereby the transmitting
and receiving lengths of signals are almost equal.

Induced currents in a perfectly balanced, routing stable
environment should cancel each other, thus eliminating crosstalk.
However, in this imperfect world that won’t happen. Therefore, the
goal must be to keep crosstalk on all the traces to as minimum a
level as possible. Crosstalk’s effect on adjacent traces can be
minimized by keeping them at least twice the trace width apart. For
example, if trace width is five mils, minimum distance between two
parallel traces should be 10 mils or more.

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Re: Tip #1 - Huh?
Allramified
8/3/2015 5:26:01 AM

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The
author need to update himself on the topic. Much water has
flown under the bridges since these rules were considered to be
valid. Several of them have also no evidence of being true, they're
just old practice without anyone knowing how and
why.

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Re: Tip #1 - Huh?
anon9303122
7/31/2015 3:52:00 PM

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Yes,
me too.   They put on a great seminar.  I was
saddened when they were putting up all their equipment for
sale.

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Re: Tip #1 - Huh?
Paul
Bryson   7/31/2015 2:17:51 PM

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I
was very sad to read that Bill Kimmel died earlier this year.
I have learned a great deal from his writing over the
years.

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Re: Tip #1 - Huh?
anon9303122
7/31/2015 12:50:06 PM

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Kimmel
and Gerke would take exception to many things in this article.
This is written by someone who knows just enough anecdotal 'tips' to
be dangerous.  Run away, run away.

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Re: Tip #1 - Huh?
Howman
7/29/2015 11:27:31 AM

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Articles
like this only reinforce the false notion that designing for
EMC is a black art.

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Re: Tip #1 - Huh?
boblespam
7/29/2015 3:06:00 AM

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I
confirm, splitting ground plane is a bad idea as you'll have nets
crossing the different planes boundaries which is very bad for the
given signal integrity and radiation.

90° angles only have an
impact on very high speed signal (steep fronts), most of the time it
has no impact on EMI.

"Decoupling capacitors reduce
crosstalk's undesirable effects": crosstalk beetween what and what
?

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Tip #1 - Huh?
Paul
Bryson   7/28/2015 5:44:14 PM

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Referring
to the paragraph in Tip #1, beginning, "The length of signal returns
to ground is highly important," and ending, "If source and return
path aren't about equal in length, ground bounce, another form of
EMI, is produced."

I can't make sense of this paragraph.
Previous paragraphs were about ground planes. Is this
paragraph talking about a signal and it's return path through the
ground plane?  The diagram seems to show return traces
surrounding a signal trace.  For EMI what matters is that the
signal and return path stay physically close together, minimizing
the loop area and the inductance.  The fact that the return
time matches the outgoing time is incidental.

The
phenomenon of "ground bounce" is usually caused when an IC tries to
quickly sink a large pulse of current into ground from an output pin
or from the supply and inductance in the ground path causes a
localized rise in the ground voltage.  What "ground bounce" is
the author referring to? In the return trace? If so then this would
again be about minimizing inductance - not matching
timing.

In another paragraph the author recommends splitting
the ground plane.  This is rarely good advice and should never
be done without following a large number of other "rules".
Otherwise, EMI will be made worse instead of
better.

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Tip #6: Use vias with care
zeeglen
7/28/2015 10:20:02 AM

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Also
remember to place an closely adjacent via connecting the power
planes wherever a high-speed via occurs.

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